1. Field of the Invention
The present invention relates to a PMOS field effect transistor and a manufacturing method thereof. In particular, the present invention relates to a vertical PMOS field effect transistor with a strained Si—Ge layer and a manufacturing method thereof.
2. Description of Related Art
In view of the manufacturing process, the MOSFET is the most popular transistor. The current transmission in the MOSFET is to form a channel along the interface to induce the current flow that is implemented by the carrier. The principle is the same as the prior transistor. When the current in the transistor is conducted by electron is called as a NMOS. When the current in the transistor is conducted by hole is called as a PMOS.
Reference is made to FIG. 1. The PMOS of the prior art includes a N-typed substrate la, a gate 2a and two gap walls 3a. The N-typed substrate 1a has a first doping area 11a and a second doping area 12a to be used as a source and a drain. On the surface of the N-typed substrate 1a, there is an oxide layer 13a. The gate 2a is located on the oxide layer 13a. The two gap walls 3a are located on the two side walls and the oxide layer 13a. However, because the source, the drain and the gate 2a of the PMOS are disposed in a plane, the transistor occupies most part of the surface area of the N-typed substrate 1a. Therefore, it is difficult to increase the element density of the semiconductor. Currently, the element density of the semiconductor is increased and the size of the transistor is reduced to produce a high density and a high performance semiconductor device. When the size of the transistor is reduced and an advanced manufacturing process is not adopted, the performance of the transistor cannot be enhanced.